1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a semiconductor memory device which has a small wiring resistance of a word line that constitutes a memory cell and is capable of being operated at high speed, and a manufacturing method thereof.
2. Description of the Prior Art
In a recent dynamic random access memory (DRAM), one memory cell is constituted of one insulated gate field effect transistor and one storage capacitor. The occupying area of the memory cell is being decreased as the memory capacity of the memory device is increased. For this reason, a method of forming a storage capacitor by stacking it in an upper layer, the so-called stacked capacitor memory cell, is being adopted in recent years as one of feasible methods for obtaining large storage capacitance for small area. With the employment of such a structure it becomes possible to increase the surface area of the capacitive electrode per unit area of the memory cell by augmenting the height of the capacitive electrode.
Moreover, in a DRAM, an improvement of the operating speed accompanying the increase in the memory capacity is also becoming necessary. As one of feasible methods for improving the operating speed, a structure which prevents the wiring delay, especially the wiring delay of word lines with large wiring length, is being employed in recent years. For example, in a paper by Sakao, et al. published before the International Electron Devices Meeting (IEDM), 1990, there is disclosed a method in which an aluminum alloy wiring with low resistance is arranged in an upper layer of a polysilicon wiring (word line) which becomes the gate electrode of the memory cell in order to reduce the wiring resistance of the polysilicon wiring, and connects the aluminum alloy wiring to the polysilicon wiring via a contact hole. According to this two-layer wiring structure it is possible to use polysilicon, which has excellent reliability though its resistance is high, as the gate electrode, and at the same time there can be obtained an effect of reducing the wiring resistance by the use of the metallic wiring.
In the above-mentioned stacked capacitor memory cell, a structure is adopted which increases the area of the side faces in addition to the area of the top surface of the capacitive storage electrode in order to obtain a large storage capacitance for a small area. Accordingly, a structure is obtained in which the height of the storage electrode part is large (1 .mu.m, for example), and the large heights difference between the memory cell array forming region and other regions (for example, the region that connects the memory cell array region and a row decoder).
When a word line is to be given a two-layer structure in such a stacked memory, the part of the metallic wiring in the upper layer in the memory cell array forming region is formed at a high position since it is formed above the capacitive storage electrode, and the difference in height of that part with the metallic wiring in the upper layer formed in other regions becomes very large. As a result, there arises a problem that disconnection in the metallic wiring is generated in this stepped part, or a problem, in the photoresist process which requires a fine pattern resolution for forming a pattern of the metallic wirings, that a pattern resolution which simultaneously satisfies the memory cell array region and other regions becomes difficult to obtain because of the difference in focusing if the height difference becomes too large.
Accordingly, although it is possible to give the two-layer structure to the portion of the word line that is in the memory cell array forming region, in other part, for example, in the portion which connects the memory cell array forming region and the row decoder forming region, one is forced to form the word line in a single layer of polysilicon alone. This leads to a large value of the word line resistance which in turn results in the problem of reduction in the operating speed of the semiconductor memory device as a whole.